1. Field of the Invention
The present invention relates to a chemical mechanical polishing (CMP) method for polishing a surface of a semiconductor wafer to thereby planarize the same in a process of producing a plurality of semiconductor devices in the semiconductor wafer, and a washing/rinsing method for removing residual substances from the polished surface of the semiconductor wafer.
2. Description of the Related Art
In a representative process of producing a plurality of semiconductor devices, for example, a silicon wafer is prepared, and a surface of the silicon wafer is sectioned into a plurality of semiconductor chip areas by forming grid-like fine grooves (i.e. scribe lines) in the silicon wafer. Then, the silicon wafer is processed by various well-known methods such that each of the semiconductor chip areas is produced as a semiconductor device. Subsequently, a multi-layered wiring arrangement is formed on the surface of the silicon wafer, using a chemical vapor deposition (CVD) process, a sputtering process, a photolithography process, an etching process, and so on.
Usually, the multi-layered wiring arrangement includes a lowermost insulating layer formed on the surface of the silicon wafer and having a plurality of metal wiring patterns formed thereon, an uppermost insulating layer having a plurality of metal wiring patterns formed thereon, and at least one insulating interlayer provided between the lowermost and uppermost insulating layers and having a plurality of metal wiring patterns. Each of the lowermost and uppermost insulating layers is formed as a silicon dioxide layer by the CVD process, and the insulating interlayer is also formed as a silicon dioxide layer by the CVD process. The formation of each plurality of metal wiring patterns is carried out by the sputtering process, the photolithography process, and the etching process, and each of the metal wiring patterns is allocated to and electrically associated with a corresponding semiconductor device on the silicon wafer through the intermediary of via-holes formed in the lowermost and uppermost insulating layers and the insulating interlayer.
When each of the semiconductor chip areas is produced as the semiconductor device, the surface of the silicon wafer is uneven. Accordingly, the lowermost insulating layer formed on the silicon wafer also exhibits unevenness, and the unevenness is gradually amplified as the silicon dioxide layers are formed in order on the lowermost insulating layer. When each plurality of metal wiring patterns are formed on the uneven surface of the corresponding silicon dioxide layer, each of the metal wiring patterns is susceptible to defects and faults, resulting in a decline in a production yield rate of the semiconductor devices.
In order to resolve this problem, whenever each of the silicon dioxide layers is formed, the surface of the silicon dioxide layer is polished, using a chemical mechanical polishing (CMP) method, to thereby planarize the same, and thus it is possible to satisfactorily carry out the formation of each plurality of metal wiring patterns on the planarized surface.
A chemical mechanical polishing (CMP) apparatus for performing the CMP method includes a rotatable disk-like platen having a polishing cloth or pad provided over a top face thereof, a rotatable carrier head disposed above the polishing pad, and an abrasive-slurry feeding nozzle for feeding aqueous abrasive slurry to the polishing pad. Note, usually, the disk-like platen has a diameter which is twice or more than that of the carrier head. The carrier head has a suction pad which can be connected to a suitable vacuum source, and the silicon wafer having the silicon dioxide layer to be polished is held by the carrier head such that the back face of the silicon wafer is sucked by the suction pad. The carrier head can be moved upward and downward with respect to the polishing pad of the disk-like platen having the diameter which is twice or more than that of the carrier head.
In a polishing operation, the disk-like platen is rotated in one rotational direction, and the carrier head carrying the silicon wafer is rotated in the same rotational direction as the disk-like platen. As the aqueous abrasive slurry is dripped from the abrasive-slurry feeding nozzle onto the polishing pad, the rotating silicon wafer is pushed against the rotating polishing pad by the carrier head, whereby the silicon dioxide layer of the silicon wafer can be polished and planarized.
With the recent advance of miniaturization of semiconductor devices, signal-transmission paths included in each metal wiring pattern become closer to each other, and thus a parasitic capacitance is produced between adjacent signal-transmission paths because the silicon dioxide layer serves as a dielectric therebetween. Of course, the production of the parasitic capacitance results in delay of signal transmission in the signal-transmission paths. In short, the miniaturization of the semiconductor devices has advanced to a degree in which a magnitude of a dielectric constant of the silicon dioxide layer cannot be neglected.
Therefore, in the process of producing the semiconductor devices, it has been proposed that an insulating layer, composed of a low-k material having a smaller dielectric constant than that of silicon dioxide, be substituted for the silicon dioxide insulating layer, to thereby suppress the production of the parasitic capacitance, as disclosed in U.S. Pat. No. 6,423,630.
Nevertheless, by the conventional CMP method, it is difficult to efficiently polish the insulating layer composed of the low-k material, because the low-k material insulating layer, such as a SiCOH layer, an MSQ (methyl silsesquioxane) layer or the like, exhibits a hydrophobic nature. Namely, as stated above, although the aqueous abrasive slurry is used in the conventional CMP method, the low-k material insulating layer repels the aqueous abrasive slurry due to the hydrophobic nature thereof, resulting in considerable decline in a polishing rate of the low-k material insulating layer.
After the low-k material insulating layer of the semiconductor wafer is polished by the CMP method, the semiconductor wafer is subjected to a washing process and a rinsing process to thereby remove the aqueous abrasive slurry together with residual substances from the polished insulating layer of the semiconductor wafer. However, the removal of the residual substances from the polished low-k material insulating layer of the semiconductor wafer is very difficult due to the hydrophobic nature thereof, as explained in detail hereinafter.